The present invention relates to computer memory interface circuitry in general, and more particularly to the sorting of requests for efficient access to memories.
Memory devices are fast becoming a bottleneck and limiting improvements in computer system performance. Part of this is caused by the relative disparity between the increase in processor as compared to memory speed. That is, while processor speed has continued to increase at the well known rate of doubling every 18 to 24 months, memory access times have not kept pace. This gap means that more efficient use of memory bandwidth must be made in order to reduce the effect of this bottleneck and take full advantage of the improved processor performance.
Data is accessed from a memory by selecting the row and column of one or more memory locations. This is done by asserting specific row and column address signals, referred to as RAS and CAS. The rows in a memory tend to be long traces with many memory cells attached. Accordingly, there is a comparatively long delay when a selected row, or page, is changed. Thus, when a row is selected, it is desirable to continue accessing different columns in that row before selecting another row. This is particularly true if the same bank in the memory is needed.
Memories in computer systems are often made up of multiple dynamic random-access-memory (DRAM) circuits, which may be located in dual-in-line memory modules (DIMMs). These DRAMs are selected using a chip select signal. When changing DRAMs, even if the same row is maintained, there is a delay while a different DRAM is selected.
Page switching overhead (resulting from “page breaks”) is inherent in DRAMs. For example in some DRAMs, each bank of DRAM has multiple pages, and to open a page may incur approximately 10 memory cycles after the page is activated. To switch to a second page requires closing the previously opened page and reopening the bank to another page. For example, since there is a non-zero amount of overhead required to change pages, increasing the number of accesses made to a page before switching to another page reduces page switching overhead.
However, in some streams of data requests, the number of accesses made to a page before switching to another page may not be able to be increased significantly. In these circumstances, poorer memory access results due to many page breaks.
Therefore, it is desirable to provide methods and systems for sorting memory requests in which the downtime during these memory breaks can be hidden or buried.